Platform specific HAL abstraction layer that abstracts the mailbox hardware interaction.
This task targets only platform abstraction for twin-cpu platforms. Architecture (v8-M / v7-M) abstraction is targeted in another task.
For communication between secure world and non secure world there are multiple configurations possible:
a. All or part of non-secure memory space is accessible to secure core - in this case, mailbox acts as a control plane, bulk buffers are copied to secure memory only when requested through psa_read() (similar flow for write path)
b. mailbox is the only channel of communication between secure and non-secure cores. In this case, all of the data is also passed over mailbox
For the PoC only option a. is targeted.