Page MenuHomePhabricator

Platarmboardfvpincludeplatform Defhvsplatarmboardfvp Rincludeplatform Defh
Updated 82 Days AgoPublic

/*                                                            /*
 * Copyright (c) 2014-2021, ARM Limited and Contributors.      * Copyright (c) 2014-2021, ARM Limited and Contributors. 
 *                                                             *
 * SPDX-License-Identifier: BSD-3-Clause                       * SPDX-License-Identifier: BSD-3-Clause
 */                                                            */

#ifndef PLATFORM_DEF_H                                        #ifndef PLATFORM_DEF_H
#define PLATFORM_DEF_H                                        #define PLATFORM_DEF_H

                                                           >  #define NO_EL3                          1
                                                           >
                                                           >  #define BL33_IMAGE_DESC {                               \
                                                           >          .image_id = BL33_IMAGE_ID,                      \
                                                           >          SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,     \
                                                           >                  VERSION_2, image_info_t, 0),            \
                                                           >          .image_info.image_base = PLAT_ARM_DRAM1_BASE + 0x1
                                                           >          .image_info.image_max_size = UL(0x3ffff000), \
                                                           >          SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,        \
                                                           >                  VERSION_2, entry_point_info_t, SECURE | EX
                                                           >          .ep_info.pc = PLAT_ARM_DRAM1_BASE + 0x1000,       
                                                           >          .ep_info.spsr =SPSR_64(MODE_EL2, MODE_SP_ELX, DISA
                                                           >  }
                                                           >
#include <drivers/arm/tzc400.h>                               #include <drivers/arm/tzc400.h>
#include <lib/utils_def.h>                                    #include <lib/utils_def.h>
                                                           >  #define PLAT_V2M_OFFSET                 0x80000000
#include <plat/arm/board/common/v2m_def.h>                    #include <plat/arm/board/common/v2m_def.h>
                                                           >
                                                           >  /* These are referenced by arm_def.h #included next, so #d
                                                           >  #define PLAT_ARM_TRUSTED_SRAM_BASE      UL(0x84000000)
                                                           >  #define PLAT_ARM_TRUSTED_SRAM_SIZE      UL(0x00040000)  /*
                                                           >
#include <plat/arm/common/arm_def.h>                          #include <plat/arm/common/arm_def.h>
#include <plat/arm/common/arm_spm_def.h>                   <
#include <plat/common/common_def.h>                           #include <plat/common/common_def.h>

#include "../fvp_def.h"                                    |  #include "../fvp_r_def.h"
                                                           >
                                                           >  /* Required to create plat_regions: */
                                                           >  #define MIN_LVL_BLOCK_DESC      U(1)

/* Required platform porting definitions */                   /* Required platform porting definitions */
#define PLATFORM_CORE_COUNT  (U(FVP_CLUSTER_COUNT) * \     |  #define PLATFORM_CORE_COUNT  (U(FVP_R_CLUSTER_COUNT) * \
                              U(FVP_MAX_CPUS_PER_CLUSTER)  |                                U(FVP_R_MAX_CPUS_PER_CLUSTER
                              U(FVP_MAX_PE_PER_CPU))       |                                U(FVP_R_MAX_PE_PER_CPU))

#define PLAT_NUM_PWR_DOMAINS (U(FVP_CLUSTER_COUNT) + \     |  #define PLAT_NUM_PWR_DOMAINS (U(FVP_R_CLUSTER_COUNT) + \
                              PLATFORM_CORE_COUNT + U(1))                                   PLATFORM_CORE_COUNT + U(1))

#define PLAT_MAX_PWR_LVL                ARM_PWR_LVL2          #define PLAT_MAX_PWR_LVL                ARM_PWR_LVL2

/*                                                            /*
 * Other platform porting definitions are provided by incl     * Other platform porting definitions are provided by incl
 */                                                            */

/*                                                            /*
 * Required ARM standard platform porting definitions          * Required ARM standard platform porting definitions
 */                                                            */
#define PLAT_ARM_CLUSTER_COUNT          U(FVP_CLUSTER_COUN |  #define PLAT_ARM_CLUSTER_COUNT          U(FVP_R_CLUSTER_CO

#define PLAT_ARM_TRUSTED_SRAM_SIZE      UL(0x00040000)  /* |  #define PLAT_ARM_DRAM1_BASE             ULL(0x0)
                                                           >  #define PLAT_ARM_DRAM1_SIZE             ULL(0x7fffffff)

#define PLAT_ARM_TRUSTED_ROM_BASE       UL(0x00000000)     |  #define PLAT_ARM_TRUSTED_ROM_BASE       UL(0x80000000)
#define PLAT_ARM_TRUSTED_ROM_SIZE       UL(0x04000000)  /*    #define PLAT_ARM_TRUSTED_ROM_SIZE       UL(0x04000000)  /*

#define PLAT_ARM_TRUSTED_DRAM_BASE      UL(0x06000000)     |  #define PLAT_ARM_TRUSTED_DRAM_BASE      UL(0x86000000)
#define PLAT_ARM_TRUSTED_DRAM_SIZE      UL(0x02000000)  /*    #define PLAT_ARM_TRUSTED_DRAM_SIZE      UL(0x02000000)  /*

/*                                                         |  /* These two are defined thus in arm_def.h, but doesn't se
 * Max size of SPMC is 2MB for fvp. With SPMD enabled this |  #define PLAT_BL1_RO_LIMIT               (BL1_RO_BASE \
 * max size of BL32 image.                                 |                                          + PLAT_ARM_TRUSTED
 */                                                        |
#if defined(SPD_spmd)                                      |  #define PLAT_ARM_SYS_CNTCTL_BASE        UL(0xaa430000)
#define PLAT_ARM_SPMC_BASE              PLAT_ARM_TRUSTED_D |  #define PLAT_ARM_SYS_CNTREAD_BASE       UL(0xaa800000)
#define PLAT_ARM_SPMC_SIZE              UL(0x200000)  /* 2 |  #define PLAT_ARM_SYS_TIMCTL_BASE        UL(0xaa810000)
#endif                                                     |  #define PLAT_ARM_SYS_CNT_BASE_S         UL(0xaa820000)
                                                           >  #define PLAT_ARM_SYS_CNT_BASE_NS        UL(0xaa830000)
                                                           >  #define PLAT_ARM_SP805_TWDG_BASE        UL(0xaa490000)
                                                           >

/* virtual address used by dynamic mem_protect for chunk_b    /* virtual address used by dynamic mem_protect for chunk_b
#define PLAT_ARM_MEM_PROTEC_VA_FRAME    UL(0xc0000000)        #define PLAT_ARM_MEM_PROTEC_VA_FRAME    UL(0xc0000000)

/* No SCP in FVP */                                        |  /* No SCP in FVP_R */
#define PLAT_ARM_SCP_TZC_DRAM1_SIZE     UL(0x0)               #define PLAT_ARM_SCP_TZC_DRAM1_SIZE     UL(0x0)

#define PLAT_ARM_DRAM2_BASE             ULL(0x880000000)   |  #define PLAT_ARM_DRAM2_BASE             ULL(0x080000000)
#define PLAT_ARM_DRAM2_SIZE             UL(0x80000000)        #define PLAT_ARM_DRAM2_SIZE             UL(0x80000000)

#define PLAT_HW_CONFIG_DTB_BASE         ULL(0x82000000)    |  #define PLAT_HW_CONFIG_DTB_BASE         ULL(0x12000000)
#define PLAT_HW_CONFIG_DTB_SIZE         ULL(0x8000)           #define PLAT_HW_CONFIG_DTB_SIZE         ULL(0x8000)

#define ARM_DTB_DRAM_NS                 MAP_REGION_FLAT(      #define ARM_DTB_DRAM_NS                 MAP_REGION_FLAT(  
                                        PLAT_HW_CONFIG_DTB                                            PLAT_HW_CONFIG_DTB
                                        PLAT_HW_CONFIG_DTB                                            PLAT_HW_CONFIG_DTB
                                        MT_MEMORY | MT_RO                                             MT_MEMORY | MT_RO 
                                                           >
                                                           >  #define V2M_FVP_R_SYSREGS_BASE          UL(0x9c010000)
                                                           >
/*                                                            /*
 * Load address of BL33 for this platform port             |   * Load address of BL33 for this platform port,
                                                           >   * U-Boot specifically must be loaded at a 4K aligned addr
 */                                                            */
#define PLAT_ARM_NS_IMAGE_BASE          (ARM_DRAM1_BASE +  |  #define PLAT_ARM_NS_IMAGE_BASE          PLAT_ARM_DRAM1_BAS

/*                                                            /*
 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries      * PLAT_ARM_MMAP_ENTRIES depends on the number of entries 
 * plat_arm_mmap array defined for each BL stage.              * plat_arm_mmap array defined for each BL stage.
 */                                                            */
#if defined(IMAGE_BL31)                                    |  #if !USE_ROMLIB
# if SPM_MM                                                <
#  define PLAT_ARM_MMAP_ENTRIES         10                 <
#  define MAX_XLAT_TABLES               9                  <
#  define PLAT_SP_IMAGE_MMAP_REGIONS    30                 <
#  define PLAT_SP_IMAGE_MAX_XLAT_TABLES 10                 <
# else                                                     <
#  define PLAT_ARM_MMAP_ENTRIES         9                  <
#  if USE_DEBUGFS                                          <
#   define MAX_XLAT_TABLES              8                  <
#  else                                                    <
#   define MAX_XLAT_TABLES              7                  <
#  endif                                                   <
# endif                                                    <
#elif defined(IMAGE_BL32)                                  <
# define PLAT_ARM_MMAP_ENTRIES          9                  <
# define MAX_XLAT_TABLES                6                  <
#elif !USE_ROMLIB                                          <
# define PLAT_ARM_MMAP_ENTRIES          11                    # define PLAT_ARM_MMAP_ENTRIES          11
# define MAX_XLAT_TABLES                5                     # define MAX_XLAT_TABLES                5
#else                                                         #else
# define PLAT_ARM_MMAP_ENTRIES          12                    # define PLAT_ARM_MMAP_ENTRIES          12
# define MAX_XLAT_TABLES                6                     # define MAX_XLAT_TABLES                6
#endif                                                        #endif
                                                           >  # define N_MPU_REGIONS                  16  /* number of M
                                                           >  # define ALL_MPU_EL2_REGIONS_USED       0xffffffff
                                                           >          /* this is the PRENR_EL2 value if all MPU regions 

/*                                                            /*
 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the curren     * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the curren
 * plus a little space for growth.                             * plus a little space for growth.
 */                                                            */
#define PLAT_ARM_MAX_BL1_RW_SIZE        UL(0xB000)            #define PLAT_ARM_MAX_BL1_RW_SIZE        UL(0xB000)

/*                                                            /*
 * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full pag     * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full pag
 */                                                            */

#if USE_ROMLIB                                                #if USE_ROMLIB
#define PLAT_ARM_MAX_ROMLIB_RW_SIZE     UL(0x1000)            #define PLAT_ARM_MAX_ROMLIB_RW_SIZE     UL(0x1000)
#define PLAT_ARM_MAX_ROMLIB_RO_SIZE     UL(0xe000)            #define PLAT_ARM_MAX_ROMLIB_RO_SIZE     UL(0xe000)
#define FVP_BL2_ROMLIB_OPTIMIZATION     UL(0x5000)         |  #define FVP_R_BL2_ROMLIB_OPTIMIZATION UL(0x6000)
#else                                                         #else
#define PLAT_ARM_MAX_ROMLIB_RW_SIZE     UL(0)                 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE     UL(0)
#define PLAT_ARM_MAX_ROMLIB_RO_SIZE     UL(0)                 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE     UL(0)
#define FVP_BL2_ROMLIB_OPTIMIZATION UL(0)                  |  #define FVP_R_BL2_ROMLIB_OPTIMIZATION UL(0)
#endif                                                        #endif

/*                                                            /*
 * PLAT_ARM_MAX_BL2_SIZE is calculated using the current B     * PLAT_ARM_MAX_BL2_SIZE is calculated using the current B
 * little space for growth.                                    * little space for growth.
 */                                                            */
#if TRUSTED_BOARD_BOOT                                        #if TRUSTED_BOARD_BOOT
#if COT_DESC_IN_DTB                                           #if COT_DESC_IN_DTB
# define PLAT_ARM_MAX_BL2_SIZE  (UL(0x1E000) - FVP_BL2_ROM |  # define PLAT_ARM_MAX_BL2_SIZE  (UL(0x1E000) - FVP_R_BL2_R
#else                                                         #else
# define PLAT_ARM_MAX_BL2_SIZE  (UL(0x1D000) - FVP_BL2_ROM |  # define PLAT_ARM_MAX_BL2_SIZE  (UL(0x1D000) - FVP_R_BL2_R
#endif                                                        #endif
#else                                                         #else
# define PLAT_ARM_MAX_BL2_SIZE  (UL(0x13000) - FVP_BL2_ROM |  # define PLAT_ARM_MAX_BL2_SIZE  (UL(0x13000) - FVP_R_BL2_R
#endif                                                        #endif

#if RESET_TO_BL31                                          <
/* Size of Trusted SRAM - the first 4KB of shared memory * <
#define PLAT_ARM_MAX_BL31_SIZE          (PLAT_ARM_TRUSTED_ <
                                         ARM_SHARED_RAM_SI <
#else                                                      <
/*                                                            /*
 * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX     * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX
 * calculated using the current BL31 PROGBITS debug size p     * calculated using the current BL31 PROGBITS debug size p
 * BL2 and BL1-RW                                              * BL2 and BL1-RW
 */                                                            */
#define PLAT_ARM_MAX_BL31_SIZE          UL(0x3D000)           #define PLAT_ARM_MAX_BL31_SIZE          UL(0x3D000)
#endif /* RESET_TO_BL31 */                                 <
                                                           <
#ifndef __aarch64__                                        <
/*                                                         <
 * Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX <
 * calculated using the current SP_MIN PROGBITS debug size <
 * BL2 and BL1-RW                                          <
 */                                                        <
# define PLAT_ARM_MAX_BL32_SIZE         UL(0x3B000)        <
#endif                                                     <

/*                                                            /*
 * Size of cacheable stacks                                    * Size of cacheable stacks
 */                                                            */
#if defined(IMAGE_BL1)                                        #if defined(IMAGE_BL1)
# if TRUSTED_BOARD_BOOT                                       # if TRUSTED_BOARD_BOOT
#  define PLATFORM_STACK_SIZE           UL(0x1000)            #  define PLATFORM_STACK_SIZE           UL(0x1000)
# else                                                        # else
#  define PLATFORM_STACK_SIZE           UL(0x500)             #  define PLATFORM_STACK_SIZE           UL(0x500)
# endif                                                       # endif
#elif defined(IMAGE_BL2)                                   <
# if TRUSTED_BOARD_BOOT                                    <
#  define PLATFORM_STACK_SIZE           UL(0x1000)         <
# else                                                     <
#  define PLATFORM_STACK_SIZE           UL(0x440)          <
# endif                                                    <
#elif defined(IMAGE_BL2U)                                  <
# define PLATFORM_STACK_SIZE            UL(0x400)          <
#elif defined(IMAGE_BL31)                                  <
#  define PLATFORM_STACK_SIZE           UL(0x800)          <
#elif defined(IMAGE_BL32)                                  <
# define PLATFORM_STACK_SIZE            UL(0x440)          <
#endif                                                        #endif

#define MAX_IO_DEVICES                  3                     #define MAX_IO_DEVICES                  3
#define MAX_IO_HANDLES                  4                     #define MAX_IO_HANDLES                  4

/* Reserve the last block of flash for PSCI MEM PROTECT fl |  /*
#define PLAT_ARM_FLASH_IMAGE_BASE       V2M_FLASH0_BASE    |   * These nominally reserve the last block of flash for PSC
#define PLAT_ARM_FLASH_IMAGE_MAX_SIZE   (V2M_FLASH0_SIZE - |   * but no PSCI in FVP_R platform, so reserve nothing:
                                                           <
#if ARM_GPT_SUPPORT                                        <
/*                                                         <
 * Offset of the FIP in the GPT image. BL1 component uses  <
 * as it does not load the partition table to get the FIP  <
 * address. At sector 34 by default (i.e. after reserved s <
 * Offset = 34 * 512(sector size) = 17408 i.e. 0x4400      <
 */                                                            */
#define PLAT_ARM_FIP_OFFSET_IN_GPT      0x4400             |  #define PLAT_ARM_FLASH_IMAGE_BASE       PLAT_ARM_DRAM1_BAS
#endif /* ARM_GPT_SUPPORT */                               |  #define PLAT_ARM_FLASH_IMAGE_MAX_SIZE   PLAT_ARM_DRAM1_SIZ

#define PLAT_ARM_NVM_BASE               V2M_FLASH0_BASE       #define PLAT_ARM_NVM_BASE               V2M_FLASH0_BASE
#define PLAT_ARM_NVM_SIZE               (V2M_FLASH0_SIZE -    #define PLAT_ARM_NVM_SIZE               (V2M_FLASH0_SIZE -

/*                                                            /*
 * PL011 related constants                                     * PL011 related constants
 */                                                            */
#define PLAT_ARM_BOOT_UART_BASE         V2M_IOFPGA_UART0_B    #define PLAT_ARM_BOOT_UART_BASE         V2M_IOFPGA_UART0_B
#define PLAT_ARM_BOOT_UART_CLK_IN_HZ    V2M_IOFPGA_UART0_C    #define PLAT_ARM_BOOT_UART_CLK_IN_HZ    V2M_IOFPGA_UART0_C

#define PLAT_ARM_RUN_UART_BASE          V2M_IOFPGA_UART1_B    #define PLAT_ARM_RUN_UART_BASE          V2M_IOFPGA_UART1_B
#define PLAT_ARM_RUN_UART_CLK_IN_HZ     V2M_IOFPGA_UART1_C    #define PLAT_ARM_RUN_UART_CLK_IN_HZ     V2M_IOFPGA_UART1_C

#define PLAT_ARM_CRASH_UART_BASE        PLAT_ARM_RUN_UART_    #define PLAT_ARM_CRASH_UART_BASE        PLAT_ARM_RUN_UART_
#define PLAT_ARM_CRASH_UART_CLK_IN_HZ   PLAT_ARM_RUN_UART_    #define PLAT_ARM_CRASH_UART_CLK_IN_HZ   PLAT_ARM_RUN_UART_

#define PLAT_ARM_TSP_UART_BASE          V2M_IOFPGA_UART2_B    #define PLAT_ARM_TSP_UART_BASE          V2M_IOFPGA_UART2_B
#define PLAT_ARM_TSP_UART_CLK_IN_HZ     V2M_IOFPGA_UART2_C    #define PLAT_ARM_TSP_UART_CLK_IN_HZ     V2M_IOFPGA_UART2_C

#define PLAT_FVP_SMMUV3_BASE            UL(0x2b400000)     <
                                                           <
/* CCI related constants */                                   /* CCI related constants */
#define PLAT_FVP_CCI400_BASE            UL(0x2c090000)     |  #define PLAT_FVP_R_CCI400_BASE          UL(0xac090000)
#define PLAT_FVP_CCI400_CLUS0_SL_PORT   3                  |  #define PLAT_FVP_R_CCI400_CLUS0_SL_PORT 3
#define PLAT_FVP_CCI400_CLUS1_SL_PORT   4                  |  #define PLAT_FVP_R_CCI400_CLUS1_SL_PORT 4

/* CCI-500/CCI-550 on Base platform */                        /* CCI-500/CCI-550 on Base platform */
#define PLAT_FVP_CCI5XX_BASE            UL(0x2a000000)     |  #define PLAT_FVP_R_CCI5XX_BASE          UL(0xaa000000)
#define PLAT_FVP_CCI5XX_CLUS0_SL_PORT   5                  |  #define PLAT_FVP_R_CCI5XX_CLUS0_SL_PORT 5
#define PLAT_FVP_CCI5XX_CLUS1_SL_PORT   6                  |  #define PLAT_FVP_R_CCI5XX_CLUS1_SL_PORT 6

/* CCN related constants. Only CCN 502 is currently suppor    /* CCN related constants. Only CCN 502 is currently suppor
#define PLAT_ARM_CCN_BASE               UL(0x2e000000)     |  #define PLAT_ARM_CCN_BASE               UL(0xae000000)
#define PLAT_ARM_CLUSTER_TO_CCN_ID_MAP  1, 5, 7, 11           #define PLAT_ARM_CLUSTER_TO_CCN_ID_MAP  1, 5, 7, 11

/* System timer related constants */                          /* System timer related constants */
#define PLAT_ARM_NSTIMER_FRAME_ID               U(1)          #define PLAT_ARM_NSTIMER_FRAME_ID               U(1)

/* Mailbox base address */                                    /* Mailbox base address */
#define PLAT_ARM_TRUSTED_MAILBOX_BASE   ARM_TRUSTED_SRAM_B    #define PLAT_ARM_TRUSTED_MAILBOX_BASE   ARM_TRUSTED_SRAM_B


/* TrustZone controller related constants                     /* TrustZone controller related constants
 *                                                             *
 * Currently only filters 0 and 2 are connected on Base FV |   * Currently only filters 0 and 2 are connected on Base FV
 * Filter 0 : CPU clusters (no access to DRAM by default)      * Filter 0 : CPU clusters (no access to DRAM by default)
 * Filter 1 : not connected                                    * Filter 1 : not connected
 * Filter 2 : LCDs (access to VRAM allowed by default)         * Filter 2 : LCDs (access to VRAM allowed by default)
 * Filter 3 : not connected                                    * Filter 3 : not connected
 * Programming unconnected filters will have no effect at      * Programming unconnected filters will have no effect at 
 * moment. These filter could, however, be connected in fu     * moment. These filter could, however, be connected in fu
 * So care should be taken not to configure the unused fil     * So care should be taken not to configure the unused fil
 *                                                             *
 * Allow only non-secure access to all DRAM to supported d     * Allow only non-secure access to all DRAM to supported d
 * Give access to the CPUs and Virtio. Some devices            * Give access to the CPUs and Virtio. Some devices
 * would normally use the default ID so allow that too.        * would normally use the default ID so allow that too.
 */                                                            */
#define PLAT_ARM_TZC_BASE               UL(0x2a4a0000)     |  #define PLAT_ARM_TZC_BASE               UL(0xaa4a0000)
#define PLAT_ARM_TZC_FILTERS            TZC_400_REGION_ATT    #define PLAT_ARM_TZC_FILTERS            TZC_400_REGION_ATT

#define PLAT_ARM_TZC_NS_DEV_ACCESS      (                     #define PLAT_ARM_TZC_NS_DEV_ACCESS      (                 
                TZC_REGION_ACCESS_RDWR(FVP_NSAID_DEFAULT)  |                  TZC_REGION_ACCESS_RDWR(FVP_R_NSAID_DEFAULT
                TZC_REGION_ACCESS_RDWR(FVP_NSAID_PCI)      |                  TZC_REGION_ACCESS_RDWR(FVP_R_NSAID_PCI)   
                TZC_REGION_ACCESS_RDWR(FVP_NSAID_AP)       |                  TZC_REGION_ACCESS_RDWR(FVP_R_NSAID_AP)    
                TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO)   |                  TZC_REGION_ACCESS_RDWR(FVP_R_NSAID_VIRTIO)
                TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO_OL |                  TZC_REGION_ACCESS_RDWR(FVP_R_NSAID_VIRTIO_

/*                                                            /*
 * GIC related constants to cater for both GICv2 and GICv3     * GIC related constants to cater for both GICv2 and GICv3
 * FVP. They could be overridden at runtime in case the FV |   * FVP_R. They could be overridden at runtime in case the 
 * legacy VE memory map.                                       * legacy VE memory map.
 */                                                            */
#define PLAT_ARM_GICD_BASE              BASE_GICD_BASE        #define PLAT_ARM_GICD_BASE              BASE_GICD_BASE
#define PLAT_ARM_GICR_BASE              BASE_GICR_BASE        #define PLAT_ARM_GICR_BASE              BASE_GICR_BASE
#define PLAT_ARM_GICC_BASE              BASE_GICC_BASE        #define PLAT_ARM_GICC_BASE              BASE_GICC_BASE

/*                                                         <
 * Define a list of Group 1 Secure and Group 0 interrupts  <
 * terminology. On a GICv2 system or mode, the lists will  <
 * as Group 0 interrupts.                                  <
 */                                                        <
#define PLAT_ARM_G1S_IRQ_PROPS(grp) \                      <
        ARM_G1S_IRQ_PROPS(grp), \                          <
        INTR_PROP_DESC(FVP_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PR <
                        GIC_INTR_CFG_LEVEL), \             <
        INTR_PROP_DESC(FVP_IRQ_SEC_SYS_TIMER, GIC_HIGHEST_ <
                        GIC_INTR_CFG_LEVEL)                <
                                                           <
#define PLAT_ARM_G0_IRQ_PROPS(grp)      ARM_G0_IRQ_PROPS(g <
                                                           <
#if SDEI_IN_FCONF                                          <
#define PLAT_SDEI_DP_EVENT_MAX_CNT      ARM_SDEI_DP_EVENT_ <
#define PLAT_SDEI_DS_EVENT_MAX_CNT      ARM_SDEI_DS_EVENT_ <
#else                                                      <
#define PLAT_ARM_PRIVATE_SDEI_EVENTS    ARM_SDEI_PRIVATE_E <
#define PLAT_ARM_SHARED_SDEI_EVENTS     ARM_SDEI_SHARED_EV <
#endif                                                     <
                                                           <
#define PLAT_ARM_SP_IMAGE_STACK_BASE    (PLAT_SP_IMAGE_NS_    #define PLAT_ARM_SP_IMAGE_STACK_BASE    (PLAT_SP_IMAGE_NS_
                                         PLAT_SP_IMAGE_NS_                                             PLAT_SP_IMAGE_NS_

#define PLAT_SP_PRI                     PLAT_RAS_PRI          #define PLAT_SP_PRI                     PLAT_RAS_PRI

/*                                                            /*
 * Physical and virtual address space limits for MMU in AA |   * Physical and virtual address space limits for MPU in AA
 */                                                            */
#ifdef __aarch64__                                         <
#define PLAT_PHY_ADDR_SPACE_SIZE        (1ULL << 36)          #define PLAT_PHY_ADDR_SPACE_SIZE        (1ULL << 36)
#define PLAT_VIRT_ADDR_SPACE_SIZE       (1ULL << 36)          #define PLAT_VIRT_ADDR_SPACE_SIZE       (1ULL << 36)
#else                                                      |
#define PLAT_PHY_ADDR_SPACE_SIZE        (1ULL << 32)       |  #define ARM_SOC_CONTINUATION_SHIFT      U(24)
#define PLAT_VIRT_ADDR_SPACE_SIZE       (1ULL << 32)       |  #define ARM_SOC_IDENTIFICATION_SHIFT    U(16)
#endif                                                     <

#endif /* PLATFORM_DEF_H */                                   #endif /* PLATFORM_DEF_H */
Last Author
garymorrison-arm
Last Edited
Jul 2 2021, 9:51 PM

Event Timeline