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Q: Multi-core reset handling
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Hi experts,
I'm trying to port TF-A and OPTEE into multi-core platform. I'm using own SPL, and I want to port BL31 only from TF-A (ROM-SPL-BL31-..)

I have 2 questions:

  1. Should I release reset of secondary cores from SPL?
  2. What address should be set for RVBAR of secondary cores?

Event Timeline

coach-bin triaged this task as Unbreak Now! priority.Jun 12 2023, 3:36 AM
coach-bin created this task.