diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Device/Source/armgcc/LPC55S69_cm33_core0_ns.ld b/platform/ext/target/nxp/lpcxpresso55s69/Device/Source/armgcc/LPC55S69_cm33_core0_ns.ld
index d5cb0957..1bfe2cb8 100755
--- a/platform/ext/target/nxp/lpcxpresso55s69/Device/Source/armgcc/LPC55S69_cm33_core0_ns.ld
+++ b/platform/ext/target/nxp/lpcxpresso55s69/Device/Source/armgcc/LPC55S69_cm33_core0_ns.ld
@@ -167,8 +167,10 @@ SECTIONS
     {
         . += __msp_stack_size__;
     } > RAM
+    Image$$ARM_LIB_STACK_MSP$$ZI$$Base = ADDR(.msp_stack);
     Image$$ARM_LIB_STACK_MSP$$ZI$$Limit = ADDR(.msp_stack) + SIZEOF(.msp_stack);
 
+
     .psp_stack : ALIGN(32)
     {
         . += __psp_stack_size__;
diff --git a/platform/ext/target/nxp/lpcxpresso55s69/spm_hal.c b/platform/ext/target/nxp/lpcxpresso55s69/spm_hal.c
index 69359c68..d5f55348 100755
--- a/platform/ext/target/nxp/lpcxpresso55s69/spm_hal.c
+++ b/platform/ext/target/nxp/lpcxpresso55s69/spm_hal.c
@@ -241,7 +241,7 @@ uint32_t tfm_spm_hal_get_ns_entry_point(void)
     return *((uint32_t *)(memory_regions.non_secure_code_start+ 4));
 }
 
-enum tfm_plat_err_t tfm_spm_hal_set_secure_irq_priority(int32_t irq_line,
+enum tfm_plat_err_t tfm_spm_hal_set_secure_irq_priority(IRQn_Type irq_line,
                                                         uint32_t priority)
 {
     uint32_t quantized_priority = priority >> (8U - __NVIC_PRIO_BITS);
@@ -249,23 +249,23 @@ enum tfm_plat_err_t tfm_spm_hal_set_secure_irq_priority(int32_t irq_line,
     return TFM_PLAT_ERR_SUCCESS;
 }
 
-void tfm_spm_hal_clear_pending_irq(int32_t irq_line)
+void tfm_spm_hal_clear_pending_irq(IRQn_Type irq_line)
 {
     NVIC_ClearPendingIRQ(irq_line);
 }
 
-void tfm_spm_hal_enable_irq(int32_t irq_line)
+void tfm_spm_hal_enable_irq(IRQn_Type irq_line)
 {
     NVIC_EnableIRQ(irq_line);
 }
 
-void tfm_spm_hal_disable_irq(int32_t irq_line)
+void tfm_spm_hal_disable_irq(IRQn_Type irq_line)
 {
     NVIC_DisableIRQ(irq_line);
 }
 
 enum irq_target_state_t tfm_spm_hal_set_irq_target_state(
-                                           int32_t irq_line,
+                                           IRQn_Type irq_line,
                                            enum irq_target_state_t target_state)
 {
     uint32_t result;
diff --git a/platform/ext/target/nxp/lpcxpresso55s69/target_cfg.c b/platform/ext/target/nxp/lpcxpresso55s69/target_cfg.c
index 0f789c05..1e9ed996 100755
--- a/platform/ext/target/nxp/lpcxpresso55s69/target_cfg.c
+++ b/platform/ext/target/nxp/lpcxpresso55s69/target_cfg.c
@@ -19,7 +19,6 @@
 #include "platform_description.h"
 #include "device_definition.h"
 #include "region_defs.h"
-#include "tfm_secure_api.h"
 #include "tfm_plat_defs.h"
 
 #include "log/tfm_assert.h"
@@ -165,7 +164,7 @@ void sau_and_idau_cfg(void)
     TZ_SAU_Enable();
 
     /* Configures SAU regions to be non-secure */
-    SAU->RNR  = TFM_NS_REGION_CODE;
+    SAU->RNR  = 0U;
     SAU->RBAR = (memory_regions.non_secure_partition_base
                 & SAU_RBAR_BADDR_Msk);
     SAU->RLAR = (memory_regions.non_secure_partition_limit
@@ -173,27 +172,27 @@ void sau_and_idau_cfg(void)
                 | SAU_RLAR_ENABLE_Msk;
 
 
-    SAU->RNR  = TFM_NS_REGION_DATA;
+    SAU->RNR  = 1U;
     SAU->RBAR = (NS_DATA_START & SAU_RBAR_BADDR_Msk);
     SAU->RLAR = (NS_DATA_LIMIT & SAU_RLAR_LADDR_Msk) | SAU_RLAR_ENABLE_Msk;
 
 
     /* Configures veneers region to be non-secure callable */
-    SAU->RNR  = TFM_NS_REGION_VENEER;
+    SAU->RNR  = 2U;
     SAU->RBAR = (memory_regions.veneer_base  & SAU_RBAR_BADDR_Msk);
     SAU->RLAR = (memory_regions.veneer_limit & SAU_RLAR_LADDR_Msk)
                 | SAU_RLAR_ENABLE_Msk
                 | SAU_RLAR_NSC_Msk;
 
     /* Configure the peripherals space */
-    SAU->RNR  = TFM_NS_REGION_PERIPH_1;
+    SAU->RNR  = 3U;
     SAU->RBAR = (PERIPHERALS_BASE_NS_START & SAU_RBAR_BADDR_Msk);
     SAU->RLAR = (PERIPHERALS_BASE_NS_END & SAU_RLAR_LADDR_Msk)
                 | SAU_RLAR_ENABLE_Msk;
 
 #ifdef BL2
     /* Secondary image partition */
-    SAU->RNR  = TFM_NS_SECONDARY_IMAGE_REGION;
+    SAU->RNR  = 4U;
     SAU->RBAR = (memory_regions.secondary_partition_base  & SAU_RBAR_BADDR_Msk);
     SAU->RLAR = (memory_regions.secondary_partition_limit & SAU_RLAR_LADDR_Msk)
                 | SAU_RLAR_ENABLE_Msk;