In TF-M project if TFM_LVL=3 then MPU is miss-configured:
- All memory region is configured as "Device".
- Some of them(code/data/stack/heap) should be "Normal"
- This cause i.e.: Unaligned access exception when CPU tries to read write from non 4 bytes aligned address. This is supported by architecture if memory is configured as "Normal", but prohibited if memory is configured as "Device"