Phriction Trusted Firmware Trusted Firmware-A (TF-A) Patchdescription Bl1bl1 Maincvsplatarmboardfvp Rfvp R Bl1 Mainc
Bl1bl1 Maincvsplatarmboardfvp Rfvp R Bl1 Mainc
Bl1bl1 Maincvsplatarmboardfvp Rfvp R Bl1 Mainc
/* <
* Copyright (c) 2013-2021, ARM Limited and Contributors. <
* <
* SPDX-License-Identifier: BSD-3-Clause <
*/ <
<
#include <assert.h> #include <assert.h>
#include <platform_def.h> #include <platform_def.h>
#include <arch.h> #include <arch.h>
> /*
> * Copyright (c) 2021, ARM Limited and Contributors. All r
> *
> * SPDX-License-Identifier: BSD-3-Clause
> */
>
#include <arch_features.h> #include <arch_features.h>
#include <arch_helpers.h> #include <arch_helpers.h>
#include <bl1/bl1.h> #include <bl1/bl1.h>
#include <plat/arm/board/fvp_r/fvp_r_bl1.h> <
#include <common/bl_common.h> #include <common/bl_common.h>
#include <common/debug.h> #include <common/debug.h>
#include <drivers/auth/auth_mod.h> #include <drivers/auth/auth_mod.h>
#include <drivers/console.h> #include <drivers/console.h>
#include <lib/cpus/errata_report.h> #include <lib/cpus/errata_report.h>
#include <lib/utils.h> #include <lib/utils.h>
> #include <plat/arm/common/plat_arm.h>
#include <plat/common/platform.h> #include <plat/common/platform.h>
#include <smccc_helpers.h> #include <smccc_helpers.h>
#include <tools_share/uuid.h> #include <tools_share/uuid.h>
#include "bl1_private.h" | #include "../../../../bl1/bl1_private.h"
static void bl1_load_bl2(void); | void bl1_run_next_image(const struct entry_point_info *bl_
<
#if ENABLE_PAUTH <
uint64_t bl1_apiakey[2]; <
#endif <
<
/********************************************************* <
* Helper utility to calculate the BL2 memory layout takin <
* the BL1 RW data assuming that it is at the top of the m <
********************************************************* <
void bl1_calc_bl2_mem_layout(const meminfo_t *bl1_mem_layo <
meminfo_t *bl2_mem_layout) <
{ <
assert(bl1_mem_layout != NULL); <
assert(bl2_mem_layout != NULL); <
<
/* <
* Remove BL1 RW data from the scope of memory vis <
* This is assuming BL1 RW data is at the top of b <
*/ <
assert(BL1_RW_BASE > bl1_mem_layout->total_base); <
bl2_mem_layout->total_base = bl1_mem_layout->total <
bl2_mem_layout->total_size = BL1_RW_BASE - bl1_mem <
<
flush_dcache_range((uintptr_t)bl2_mem_layout, size <
} <
<
/********************************************************* <
* Setup function for BL1. <
********************************************************* <
void bl1_setup(void) <
{ <
/* Perform early platform-specific setup */ <
bl1_early_platform_setup(); <
<
/* Perform late platform-specific setup */ <
bl1_plat_arch_setup(); <
<
#if CTX_INCLUDE_PAUTH_REGS <
/* <
* Assert that the ARMv8.3-PAuth registers are pre <
* fault will be triggered when they are being sav <
*/ <
assert(is_armv8_3_pauth_present()); <
#endif /* CTX_INCLUDE_PAUTH_REGS */ <
} <
/********************************************************* /*********************************************************
* Function to perform late architectural and platform spe * Function to perform late architectural and platform spe
* It also queries the platform to load and run next BL im * It also queries the platform to load and run next BL im
* by the primary cpu after a cold boot. * by the primary cpu after a cold boot.
********************************************************* *********************************************************
void bl1_main(void) | void bl1_transfer_bl33 (void)
{ {
unsigned int image_id; unsigned int image_id;
/* Announce our arrival */ | /* Get the image id of next image to load and run.
NOTICE(FIRMWARE_WELCOME_STR); | image_id = bl1_plat_get_next_image_id();
NOTICE("BL1: %s\n", version_string); <
NOTICE("BL1: %s\n", build_message); <
<
INFO("BL1: RAM %p - %p\n", (void *)BL1_RAM_BASE, ( <
<
print_errata_status(); <
#if ENABLE_ASSERTIONS | #if ENABLE_PAUTH
u_register_t val; <
/* <
* Ensure that MMU/Caches and coherency are turned <
*/ <
#ifndef NO_EL3 <
#ifdef __aarch64__ <
val = read_sctlr_el3(); <
#else <
val = read_sctlr(); <
#endif <
#else /* def NO_EL3 */ <
val = read_sctlr_el2(); <
#endif /* ifndef NO_EL3 */ <
<
assert((val & SCTLR_M_BIT) != 0); <
assert((val & SCTLR_C_BIT) != 0); <
assert((val & SCTLR_I_BIT) != 0); <
/* <
* Check that Cache Writeback Granule (CWG) in CTR <
* provided platform value <
*/ <
val = (read_ctr_el0() >> CTR_CWG_SHIFT) & CTR_CWG_ <
/* /*
* If CWG is zero, then no CWG information is avai | * Disable pointer authentication before running n
* at least check the platform value is less than <
* maximum. <
*/ */
if (val != 0) | pauth_disable_el2();
assert(CACHE_WRITEBACK_GRANULE == SIZE_FRO <
else <
assert(CACHE_WRITEBACK_GRANULE <= MAX_CACH <
#endif /* ENABLE_ASSERTIONS */ <
<
/* Perform remaining generic architectural setup f <
bl1_arch_setup(); <
<
#if TRUSTED_BOARD_BOOT <
/* Initialize authentication module */ <
auth_mod_init(); <
#endif /* TRUSTED_BOARD_BOOT */ <
<
/* Perform platform setup in BL1. */ <
bl1_platform_setup(); <
<
#if ENABLE_PAUTH <
/* Store APIAKey_EL1 key */ <
bl1_apiakey[0] = read_apiakeylo_el1(); <
bl1_apiakey[1] = read_apiakeyhi_el1(); <
#endif /* ENABLE_PAUTH */ #endif /* ENABLE_PAUTH */
/* Get the image id of next image to load and run. | #if !ARM_DISABLE_TRUSTED_WDOG
image_id = bl1_plat_get_next_image_id(); | /* Disable watchdog before leaving BL1 */
> plat_arm_secure_wdt_stop();
> #endif
/* | bl1_run_next_image(&bl1_plat_get_image_desc(image_
* We currently interpret any image id other than <
* BL2_IMAGE_ID as the start of firmware update. <
*/ <
if (image_id == BL2_IMAGE_ID) <
bl1_load_bl2(); <
#ifdef NO_EL3 <
else if (image_id == BL33_IMAGE_ID) <
bl1_load_bl33(); <
#endif /* NO_EL3 */ <
else <
NOTICE("BL1-FWU: *******FWU Process Starte <
<
bl1_prepare_next_image(image_id); <
<
console_flush(); <
<
#ifdef NO_EL3 <
bl1_transfer_bl33(); <
#endif /* NO_EL3 */ <
} }
/********************************************************* /*********************************************************
* This function locates and loads the BL2 raw binary imag | * This function locates and loads the BL33 raw binary ima
* Called by the primary cpu after a cold boot. * Called by the primary cpu after a cold boot.
* TODO: Add support for alternative image load mechanism * TODO: Add support for alternative image load mechanism
* loader etc. * loader etc.
********************************************************* *********************************************************
static void bl1_load_bl2(void) | void bl1_load_bl33(void)
{ {
image_desc_t *desc; image_desc_t *desc;
image_info_t *info; image_info_t *info;
int err; int err;
/* Get the image descriptor */ /* Get the image descriptor */
desc = bl1_plat_get_image_desc(BL2_IMAGE_ID); | desc = bl1_plat_get_image_desc(BL33_IMAGE_ID);
assert(desc != NULL); assert(desc != NULL);
/* Get the image info */ /* Get the image info */
info = &desc->image_info; info = &desc->image_info;
INFO("BL1: Loading BL2\n"); | INFO("BL1: Loading BL33\n");
err = bl1_plat_handle_pre_image_load(BL2_IMAGE_ID) | err = bl1_plat_handle_pre_image_load(BL33_IMAGE_ID
if (err != 0) { if (err != 0) {
ERROR("Failure in pre image load handling | ERROR("Failure in pre image load handling
plat_error_handler(err); plat_error_handler(err);
} }
err = load_auth_image(BL2_IMAGE_ID, info); | err = load_auth_image(BL33_IMAGE_ID, info);
if (err != 0) { if (err != 0) {
ERROR("Failed to load BL2 firmware.\n"); | ERROR("Failed to load BL33 firmware.\n");
plat_error_handler(err); plat_error_handler(err);
} }
/* Allow platform to handle image information. */ /* Allow platform to handle image information. */
err = bl1_plat_handle_post_image_load(BL2_IMAGE_ID | err = bl1_plat_handle_post_image_load(BL33_IMAGE_I
if (err != 0) { if (err != 0) {
ERROR("Failure in post image load handling | ERROR("Failure in post image load handling
plat_error_handler(err); plat_error_handler(err);
} }
NOTICE("BL1: Booting BL2\n"); | NOTICE("BL1: Booting BL33\n");
} <
<
/********************************************************* <
* Function called just before handing over to the next BL <
* about the boot progress. In debug mode, also print deta <
* image's execution context. <
********************************************************* <
void bl1_print_next_bl_ep_info(const entry_point_info_t *b <
{ <
#ifdef __aarch64__ <
NOTICE("BL1: Booting BL31\n"); <
#else <
NOTICE("BL1: Booting BL32\n"); <
#endif /* __aarch64__ */ <
print_entry_point_info(bl_ep_info); <
} <
<
#if SPIN_ON_BL1_EXIT <
void print_debug_loop_message(void) <
{ <
NOTICE("BL1: Debug loop, spinning forever\n"); <
NOTICE("BL1: Please connect the debugger to contin <
} <
#endif <
<
/********************************************************* <
* Top level handler for servicing BL1 SMCs. <
********************************************************* <
u_register_t bl1_smc_handler(unsigned int smc_fid, <
u_register_t x1, <
u_register_t x2, <
u_register_t x3, <
u_register_t x4, <
void *cookie, <
void *handle, <
unsigned int flags) <
{ <
/* BL1 Service UUID */ <
DEFINE_SVC_UUID2(bl1_svc_uid, <
U(0xd46739fd), 0xcb72, 0x9a4d, 0xb5, 0x75, <
0x67, 0x15, 0xd6, 0xf4, 0xbb, 0x4a); <
<
<
#if TRUSTED_BOARD_BOOT <
/* <
* Dispatch FWU calls to FWU SMC handler and retur <
* value <
*/ <
if (is_fwu_fid(smc_fid)) { <
return bl1_fwu_smc_handler(smc_fid, x1, x2 <
handle, flags); <
} <
#endif <
<
switch (smc_fid) { <
case BL1_SMC_CALL_COUNT: <
SMC_RET1(handle, BL1_NUM_SMC_CALLS); <
<
case BL1_SMC_UID: <
SMC_UUID_RET(handle, bl1_svc_uid); <
<
case BL1_SMC_VERSION: <
SMC_RET1(handle, BL1_SMC_MAJOR_VER | BL1_S <
<
default: <
WARN("Unimplemented BL1 SMC Call: 0x%x\n", <
SMC_RET1(handle, SMC_UNK); <
} <
} <
<
/********************************************************* <
* BL1 SMC wrapper. This function is only used in AArch32 <
* compliance when invoking bl1_smc_handler. <
********************************************************* <
u_register_t bl1_smc_wrapper(uint32_t smc_fid, <
void *cookie, <
void *handle, <
unsigned int flags) <
{ <
u_register_t x1, x2, x3, x4; <
<
assert(handle != NULL); <
<
get_smc_params_from_ctx(handle, x1, x2, x3, x4); <
return bl1_smc_handler(smc_fid, x1, x2, x3, x4, co <
} }Tags
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- Last Author
- garymorrison-arm
- Last Edited
- Jul 2 2021, 11:06 PM