Phriction Trusted Firmware Trusted Firmware-A (TF-A) Patchdescription Platarmboardfvpfvp Commoncvsplatarmboardfvp Rfvp R Commonc
Platarmboardfvpfvp Commoncvsplatarmboardfvp Rfvp R Commonc
Platarmboardfvpfvp Commoncvsplatarmboardfvp Rfvp R Commonc
/* /*
* Copyright (c) 2013-2021, ARM Limited and Contributors. | * Copyright (c) 2021, ARM Limited and Contributors. All r
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
#include <assert.h> #include <assert.h>
> /* This uses xlat_mpu, but tables are set up using V2 mmap
> #define XLAT_TABLES_LIB_V2 1
#include <common/debug.h> #include <common/debug.h>
#include <drivers/arm/cci.h> #include <drivers/arm/cci.h>
#include <drivers/arm/ccn.h> #include <drivers/arm/ccn.h>
#include <drivers/arm/gicv2.h> #include <drivers/arm/gicv2.h>
#include <drivers/arm/sp804_delay_timer.h> #include <drivers/arm/sp804_delay_timer.h>
#include <drivers/generic_delay_timer.h> #include <drivers/generic_delay_timer.h>
#include <lib/mmio.h> #include <lib/mmio.h>
#include <lib/smccc.h> #include <lib/smccc.h>
#include <lib/xlat_tables/xlat_tables_compat.h> #include <lib/xlat_tables/xlat_tables_compat.h>
#include <platform_def.h> #include <platform_def.h>
#include <services/arm_arch_svc.h> #include <services/arm_arch_svc.h>
#if SPM_MM <
#include <services/spm_mm_partition.h> <
#endif <
#include <plat/arm/common/arm_config.h> #include <plat/arm/common/arm_config.h>
#include <plat/arm/common/plat_arm.h> #include <plat/arm/common/plat_arm.h>
#include <plat/common/platform.h> #include <plat/common/platform.h>
#include "fvp_private.h" | #include "fvp_r_private.h"
/* Defines for GIC Driver build time selection */ /* Defines for GIC Driver build time selection */
#define FVP_GICV2 1 | #define FVP_R_GICV3 2
#define FVP_GICV3 2 <
/********************************************************* /*********************************************************
* arm_config holds the characteristics of the differences | * arm_config holds the characteristics of the differences
* platforms (Base, A53_A57 & Foundation). It will be popu | * platforms. It will be populated during cold boot at eac
* at each boot stage by the primary before enabling the M | * primary before enabling the MPU (to allow interconnect
* interconnect configuration) & used thereafter. Each BL | * used thereafter. Each BL will have its own copy to allo
* to allow independent operation. | * operation.
********************************************************* *********************************************************
arm_config_t arm_config; arm_config_t arm_config;
#define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, #define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE,
DEVICE0_SIZE, DEVICE0_SIZE,
MT_DEVICE | MT_RW MT_DEVICE | MT_RW
#define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, #define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE,
DEVICE1_SIZE, DEVICE1_SIZE,
MT_DEVICE | MT_RW MT_DEVICE | MT_RW
#if FVP_GICR_REGION_PROTECTION <
#define MAP_GICD_MEM MAP_REGION_FLAT(BASE_GICD_BASE, <
BASE_GICD_SIZE, <
MT_DEVICE | MT_RW <
<
/* Map all core's redistributor memory as read-only. After <
* per-core map its redistributor memory as read-write */ <
#define MAP_GICR_MEM MAP_REGION_FLAT(BASE_GICR_BASE, <
(BASE_GICR_SIZE * <
MT_DEVICE | MT_RO <
#endif /* FVP_GICR_REGION_PROTECTION */ <
<
/* /*
* Need to be mapped with write permissions in order to se * Need to be mapped with write permissions in order to se
* counter value. * counter value.
*/ */
#define MAP_DEVICE2 MAP_REGION_FLAT(DEVICE2_BASE, #define MAP_DEVICE2 MAP_REGION_FLAT(DEVICE2_BASE,
DEVICE2_SIZE, DEVICE2_SIZE,
MT_DEVICE | MT_RW MT_DEVICE | MT_RW
/* /*
* Table of memory regions for various BL stages to map us | * Table of memory regions for various BL stages to map us
* This doesn't include Trusted SRAM as setup_page_tables( * This doesn't include Trusted SRAM as setup_page_tables(
* of mapping it. * of mapping it.
* *
* The flash needs to be mapped as writable in order to er * The flash needs to be mapped as writable in order to er
* Contents in case of unrecoverable error (see plat_error * Contents in case of unrecoverable error (see plat_error
*/ */
#ifdef IMAGE_BL1 #ifdef IMAGE_BL1
const mmap_region_t plat_arm_mmap[] = { const mmap_region_t plat_arm_mmap[] = {
ARM_MAP_SHARED_RAM, ARM_MAP_SHARED_RAM,
V2M_MAP_FLASH0_RW, V2M_MAP_FLASH0_RW,
V2M_MAP_IOFPGA, V2M_MAP_IOFPGA,
MAP_DEVICE0, MAP_DEVICE0,
#if FVP_INTERCONNECT_DRIVER == FVP_CCN <
MAP_DEVICE1, MAP_DEVICE1,
#endif <
#if TRUSTED_BOARD_BOOT <
/* To access the Root of Trust Public Key register <
MAP_DEVICE2, <
/* Map DRAM to authenticate NS_BL2U image. */ <
ARM_MAP_NS_DRAM1, <
#endif <
{0} <
}; <
#endif <
#ifdef IMAGE_BL2 <
const mmap_region_t plat_arm_mmap[] = { <
ARM_MAP_SHARED_RAM, <
V2M_MAP_FLASH0_RW, <
V2M_MAP_IOFPGA, <
MAP_DEVICE0, <
#if FVP_INTERCONNECT_DRIVER == FVP_CCN <
MAP_DEVICE1, <
#endif <
ARM_MAP_NS_DRAM1, <
#ifdef __aarch64__ <
ARM_MAP_DRAM2, <
#endif <
#if defined(SPD_spmd) <
ARM_MAP_TRUSTED_DRAM, <
#endif <
#ifdef SPD_tspd <
ARM_MAP_TSP_SEC_MEM, <
#endif <
#if TRUSTED_BOARD_BOOT #if TRUSTED_BOARD_BOOT
/* To access the Root of Trust Public Key register /* To access the Root of Trust Public Key register
MAP_DEVICE2, MAP_DEVICE2,
#if !BL2_AT_EL3 <
ARM_MAP_BL1_RW, <
#endif <
#endif /* TRUSTED_BOARD_BOOT */ <
#if SPM_MM <
ARM_SP_IMAGE_MMAP, <
#endif <
#if ARM_BL31_IN_DRAM <
ARM_MAP_BL31_SEC_DRAM, <
#endif <
#ifdef SPD_opteed <
ARM_MAP_OPTEE_CORE_MEM, <
ARM_OPTEE_PAGEABLE_LOAD_MEM, <
#endif <
{0} <
}; <
#endif <
#ifdef IMAGE_BL2U <
const mmap_region_t plat_arm_mmap[] = { <
MAP_DEVICE0, <
V2M_MAP_IOFPGA, <
{0} <
}; <
#endif <
#ifdef IMAGE_BL31 <
const mmap_region_t plat_arm_mmap[] = { <
ARM_MAP_SHARED_RAM, <
#if USE_DEBUGFS <
/* Required by devfip, can be removed if devfip is <
V2M_MAP_FLASH0_RW, <
#endif /* USE_DEBUGFS */ <
ARM_MAP_EL3_TZC_DRAM, <
V2M_MAP_IOFPGA, <
MAP_DEVICE0, <
#if FVP_GICR_REGION_PROTECTION <
MAP_GICD_MEM, <
MAP_GICR_MEM, <
#else <
MAP_DEVICE1, <
#endif /* FVP_GICR_REGION_PROTECTION */ <
ARM_V2M_MAP_MEM_PROTECT, <
#if SPM_MM <
ARM_SPM_BUF_EL3_MMAP, <
#endif #endif
/* Required by fconf APIs to read HW_CONFIG dtb lo <
ARM_DTB_DRAM_NS, <
{0} <
}; <
<
#if defined(IMAGE_BL31) && SPM_MM <
const mmap_region_t plat_arm_secure_partition_mmap[] = { <
V2M_MAP_IOFPGA_EL0, /* for the UART */ <
MAP_REGION_FLAT(DEVICE0_BASE, <
DEVICE0_SIZE, <
MT_DEVICE | MT_RO | MT_SECURE | MT <
ARM_SP_IMAGE_MMAP, <
ARM_SP_IMAGE_NS_BUF_MMAP, <
ARM_SP_IMAGE_RW_MMAP, <
ARM_SPM_BUF_EL0_MMAP, <
{0} <
}; <
#endif <
#endif <
#ifdef IMAGE_BL32 <
const mmap_region_t plat_arm_mmap[] = { <
#ifndef __aarch64__ <
ARM_MAP_SHARED_RAM, <
ARM_V2M_MAP_MEM_PROTECT, <
#endif <
V2M_MAP_IOFPGA, <
MAP_DEVICE0, <
MAP_DEVICE1, <
/* Required by fconf APIs to read HW_CONFIG dtb lo <
ARM_DTB_DRAM_NS, <
{0} {0}
}; };
#endif #endif
ARM_CASSERT_MMAP ARM_CASSERT_MMAP
#if FVP_INTERCONNECT_DRIVER != FVP_CCN | #if FVP_R_INTERCONNECT_DRIVER != FVP_R_CCN
static const int fvp_cci400_map[] = { static const int fvp_cci400_map[] = {
PLAT_FVP_CCI400_CLUS0_SL_PORT, | PLAT_FVP_R_CCI400_CLUS0_SL_PORT,
PLAT_FVP_CCI400_CLUS1_SL_PORT, | PLAT_FVP_R_CCI400_CLUS1_SL_PORT,
}; };
static const int fvp_cci5xx_map[] = { static const int fvp_cci5xx_map[] = {
PLAT_FVP_CCI5XX_CLUS0_SL_PORT, | PLAT_FVP_R_CCI5XX_CLUS0_SL_PORT,
PLAT_FVP_CCI5XX_CLUS1_SL_PORT, | PLAT_FVP_R_CCI5XX_CLUS1_SL_PORT,
}; };
static unsigned int get_interconnect_master(void) static unsigned int get_interconnect_master(void)
{ {
unsigned int master; unsigned int master;
u_register_t mpidr; u_register_t mpidr;
mpidr = read_mpidr_el1(); mpidr = read_mpidr_el1();
master = ((arm_config.flags & ARM_CONFIG_FVP_SHIFT master = ((arm_config.flags & ARM_CONFIG_FVP_SHIFT
MPIDR_AFFLVL2_VAL(mpidr) : MPIDR_AFFLVL1_V MPIDR_AFFLVL2_VAL(mpidr) : MPIDR_AFFLVL1_V
assert(master < FVP_CLUSTER_COUNT); | assert(master < FVP_R_CLUSTER_COUNT);
return master; return master;
} }
#endif #endif
#if defined(IMAGE_BL31) && SPM_MM <
/* <
* Boot information passed to a secure partition during in <
* indices in MP information will be filled at runtime. <
*/ <
static spm_mm_mp_info_t sp_mp_info[] = { <
[0] = {0x80000000, 0}, <
[1] = {0x80000001, 0}, <
[2] = {0x80000002, 0}, <
[3] = {0x80000003, 0}, <
[4] = {0x80000100, 0}, <
[5] = {0x80000101, 0}, <
[6] = {0x80000102, 0}, <
[7] = {0x80000103, 0}, <
}; <
<
const spm_mm_boot_info_t plat_arm_secure_partition_boot_in <
.h.type = PARAM_SP_IMAGE_BOOT_INFO, <
.h.version = VERSION_1, <
.h.size = sizeof(spm_mm_boot_info_t), <
.h.attr = 0, <
.sp_mem_base = ARM_SP_IMAGE_BASE, <
.sp_mem_limit = ARM_SP_IMAGE_LIMIT, <
.sp_image_base = ARM_SP_IMAGE_BASE, <
.sp_stack_base = PLAT_SP_IMAGE_STACK_BASE, <
.sp_heap_base = ARM_SP_IMAGE_HEAP_BASE, <
.sp_ns_comm_buf_base = PLAT_SP_IMAGE_NS_BUF_BASE, <
.sp_shared_buf_base = PLAT_SPM_BUF_BASE, <
.sp_image_size = ARM_SP_IMAGE_SIZE, <
.sp_pcpu_stack_size = PLAT_SP_IMAGE_STACK_PCPU_SI <
.sp_heap_size = ARM_SP_IMAGE_HEAP_SIZE, <
.sp_ns_comm_buf_size = PLAT_SP_IMAGE_NS_BUF_SIZE, <
.sp_shared_buf_size = PLAT_SPM_BUF_SIZE, <
.num_sp_mem_regions = ARM_SP_IMAGE_NUM_MEM_REGION <
.num_cpus = PLATFORM_CORE_COUNT, <
.mp_info = &sp_mp_info[0], <
}; <
<
const struct mmap_region *plat_get_secure_partition_mmap(v <
{ <
return plat_arm_secure_partition_mmap; <
} <
<
const struct spm_mm_boot_info *plat_get_secure_partition_b <
void *cookie) <
{ <
return &plat_arm_secure_partition_boot_info; <
} <
#endif <
<
/********************************************************* /*********************************************************
* A single boot loader stack is expected to work on both | * Initialize the platform config for future decision maki
* models and the two flavours of the Base FVP models (AEM <
* SYS_ID register provides a mechanism for detecting the <
* these platforms. This information is stored in a per-BL <
* code to take the correct path.Per BL platform configura <
********************************************************* *********************************************************
void __init fvp_config_setup(void) void __init fvp_config_setup(void)
{ {
unsigned int rev, hbi, bld, arch, sys_id; unsigned int rev, hbi, bld, arch, sys_id;
sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_I | arm_config.flags |= ARM_CONFIG_BASE_MMAP;
> sys_id = mmio_read_32(V2M_FVP_R_SYSREGS_BASE + V2M
rev = (sys_id >> V2M_SYS_ID_REV_SHIFT) & V2M_SYS_I rev = (sys_id >> V2M_SYS_ID_REV_SHIFT) & V2M_SYS_I
hbi = (sys_id >> V2M_SYS_ID_HBI_SHIFT) & V2M_SYS_I hbi = (sys_id >> V2M_SYS_ID_HBI_SHIFT) & V2M_SYS_I
bld = (sys_id >> V2M_SYS_ID_BLD_SHIFT) & V2M_SYS_I bld = (sys_id >> V2M_SYS_ID_BLD_SHIFT) & V2M_SYS_I
arch = (sys_id >> V2M_SYS_ID_ARCH_SHIFT) & V2M_SYS arch = (sys_id >> V2M_SYS_ID_ARCH_SHIFT) & V2M_SYS
if (arch != ARCH_MODEL) { if (arch != ARCH_MODEL) {
ERROR("This firmware is for FVP models\n") | ERROR("This firmware is for FVP_R models\n
panic(); panic();
} }
/* /*
* The build field in the SYS_ID tells which varia * The build field in the SYS_ID tells which varia
* memory is implemented by the model. * memory is implemented by the model.
*/ */
switch (bld) { switch (bld) {
case BLD_GIC_VE_MMAP: case BLD_GIC_VE_MMAP:
ERROR("Legacy Versatile Express memory map ERROR("Legacy Versatile Express memory map
" is not supported\n"); " is not supported\n");
panic(); panic();
break; break;
case BLD_GIC_A53A57_MMAP: case BLD_GIC_A53A57_MMAP:
break; break;
default: default:
ERROR("Unsupported board build %x\n", bld) ERROR("Unsupported board build %x\n", bld)
panic(); panic();
} }
/* /*
* The hbi field in the SYS_ID is 0x020 for the Ba | * The hbi field in the SYS_ID is 0x020 for the Ba
* for the Foundation FVP. | * for the Foundation FVP_R.
*/ */
switch (hbi) { switch (hbi) {
case HBI_FOUNDATION_FVP: | case HBI_FOUNDATION_FVP_R:
arm_config.flags = 0; arm_config.flags = 0;
/* /*
* Check for supported revisions of Founda | * Check for supported revisions of Founda
* Allow future revisions to run but emit * Allow future revisions to run but emit
*/ */
switch (rev) { switch (rev) {
case REV_FOUNDATION_FVP_V2_0: | case REV_FOUNDATION_FVP_R_V2_0:
case REV_FOUNDATION_FVP_V2_1: | case REV_FOUNDATION_FVP_R_V2_1:
case REV_FOUNDATION_FVP_v9_1: | case REV_FOUNDATION_FVP_R_v9_1:
case REV_FOUNDATION_FVP_v9_6: | case REV_FOUNDATION_FVP_R_v9_6:
break; break;
default: default:
WARN("Unrecognized Foundation FVP | WARN("Unrecognized Foundation FVP_
break; break;
} }
break; break;
case HBI_BASE_FVP: | case HBI_BASE_FVP_R:
arm_config.flags |= (ARM_CONFIG_BASE_MMAP arm_config.flags |= (ARM_CONFIG_BASE_MMAP
/* /*
* Check for supported revisions * Check for supported revisions
* Allow future revisions to run but emit * Allow future revisions to run but emit
*/ */
switch (rev) { switch (rev) {
case REV_BASE_FVP_V0: | case REV_BASE_FVP_R_V0:
arm_config.flags |= ARM_CONFIG_FVP arm_config.flags |= ARM_CONFIG_FVP
break; break;
case REV_BASE_FVP_REVC: <
arm_config.flags |= (ARM_CONFIG_FV <
ARM_CONFIG_FVP_HAS <
break; <
default: default:
WARN("Unrecognized Base FVP revisi | WARN("Unrecognized Base FVP_R revi
break; break;
} }
break; break;
default: default:
ERROR("Unsupported board HBI number 0x%x\n ERROR("Unsupported board HBI number 0x%x\n
panic(); panic();
} }
/* /*
* We assume that the presence of MT bit, and ther * We assume that the presence of MT bit, and ther
* affinities, is uniform across the platform: eit * affinities, is uniform across the platform: eit
* CPUs implement it. * CPUs implement it.
*/ */
if ((read_mpidr_el1() & MPIDR_MT_MASK) != 0U) if ((read_mpidr_el1() & MPIDR_MT_MASK) != 0U)
arm_config.flags |= ARM_CONFIG_FVP_SHIFTED arm_config.flags |= ARM_CONFIG_FVP_SHIFTED
} }
void __init fvp_interconnect_init(void) void __init fvp_interconnect_init(void)
{ {
#if FVP_INTERCONNECT_DRIVER == FVP_CCN | #if FVP_R_INTERCONNECT_DRIVER == FVP_R_CCN
if (ccn_get_part0_id(PLAT_ARM_CCN_BASE) != CCN_502 if (ccn_get_part0_id(PLAT_ARM_CCN_BASE) != CCN_502
ERROR("Unrecognized CCN variant detected. ERROR("Unrecognized CCN variant detected.
panic(); panic();
} }
plat_arm_interconnect_init(); plat_arm_interconnect_init();
#else #else
uintptr_t cci_base = 0U; uintptr_t cci_base = 0U;
const int *cci_map = NULL; const int *cci_map = NULL;
unsigned int map_size = 0U; unsigned int map_size = 0U;
/* Initialize the right interconnect */ /* Initialize the right interconnect */
if ((arm_config.flags & ARM_CONFIG_FVP_HAS_CCI5XX) if ((arm_config.flags & ARM_CONFIG_FVP_HAS_CCI5XX)
cci_base = PLAT_FVP_CCI5XX_BASE; | cci_base = PLAT_FVP_R_CCI5XX_BASE;
cci_map = fvp_cci5xx_map; cci_map = fvp_cci5xx_map;
map_size = ARRAY_SIZE(fvp_cci5xx_map); map_size = ARRAY_SIZE(fvp_cci5xx_map);
} else if ((arm_config.flags & ARM_CONFIG_FVP_HAS_ } else if ((arm_config.flags & ARM_CONFIG_FVP_HAS_
cci_base = PLAT_FVP_CCI400_BASE; | cci_base = PLAT_FVP_R_CCI400_BASE;
cci_map = fvp_cci400_map; cci_map = fvp_cci400_map;
map_size = ARRAY_SIZE(fvp_cci400_map); map_size = ARRAY_SIZE(fvp_cci400_map);
} else { } else {
return; return;
} }
assert(cci_base != 0U); assert(cci_base != 0U);
assert(cci_map != NULL); assert(cci_map != NULL);
cci_init(cci_base, cci_map, map_size); cci_init(cci_base, cci_map, map_size);
#endif #endif
} }
void fvp_interconnect_enable(void) void fvp_interconnect_enable(void)
{ {
#if FVP_INTERCONNECT_DRIVER == FVP_CCN | #if FVP_R_INTERCONNECT_DRIVER == FVP_R_CCN
plat_arm_interconnect_enter_coherency(); plat_arm_interconnect_enter_coherency();
#else #else
unsigned int master; unsigned int master;
if ((arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 if ((arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400
ARM_CONFIG_FVP_HAS_CCI5XX ARM_CONFIG_FVP_HAS_CCI5XX
master = get_interconnect_master(); master = get_interconnect_master();
cci_enable_snoop_dvm_reqs(master); cci_enable_snoop_dvm_reqs(master);
} }
#endif #endif
} }
void fvp_interconnect_disable(void) void fvp_interconnect_disable(void)
{ {
#if FVP_INTERCONNECT_DRIVER == FVP_CCN | #if FVP_R_INTERCONNECT_DRIVER == FVP_R_CCN
plat_arm_interconnect_exit_coherency(); plat_arm_interconnect_exit_coherency();
#else #else
unsigned int master; unsigned int master;
if ((arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 if ((arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400
ARM_CONFIG_FVP_HAS_CCI5XX ARM_CONFIG_FVP_HAS_CCI5XX
master = get_interconnect_master(); master = get_interconnect_master();
cci_disable_snoop_dvm_reqs(master); cci_disable_snoop_dvm_reqs(master);
} }
#endif #endif
} }
#if TRUSTED_BOARD_BOOT #if TRUSTED_BOARD_BOOT
int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_s int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_s
{ {
assert(heap_addr != NULL); assert(heap_addr != NULL);
assert(heap_size != NULL); assert(heap_size != NULL);
return arm_get_mbedtls_heap(heap_addr, heap_size); return arm_get_mbedtls_heap(heap_addr, heap_size);
} }
#endif #endif
void fvp_timer_init(void) void fvp_timer_init(void)
{ {
#if USE_SP804_TIMER #if USE_SP804_TIMER
/* Enable the clock override for SP804 timer 0, wh /* Enable the clock override for SP804 timer 0, wh
* clock dividers are applied and the raw (35MHz) * clock dividers are applied and the raw (35MHz)
*/ */
mmio_write_32(V2M_SP810_BASE, FVP_SP810_CTRL_TIM0_ | mmio_write_32(V2M_SP810_BASE, FVP_R_SP810_CTRL_TIM
/* Initialize delay timer driver using SP804 dual /* Initialize delay timer driver using SP804 dual
sp804_timer_init(V2M_SP804_TIMER0_BASE, sp804_timer_init(V2M_SP804_TIMER0_BASE,
SP804_TIMER_CLKMULT, SP804_TIMER_C SP804_TIMER_CLKMULT, SP804_TIMER_C
#else #else
generic_delay_timer_init(); generic_delay_timer_init();
/* Enable System level generic timer */ /* Enable System level generic timer */
mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF, mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF,
CNTCR_FCREQ(0U) | CNTCR_EN); CNTCR_FCREQ(0U) | CNTCR_EN);
#endif /* USE_SP804_TIMER */ #endif /* USE_SP804_TIMER */
} }
/********************************************************* <
* plat_is_smccc_feature_available() - This function check <
* feature is availabi <
* @fid: SMCCC function id <
* <
* Return SMC_ARCH_CALL_SUCCESS if SMCCC feature is availa <
* SMC_ARCH_CALL_NOT_SUPPORTED otherwise. <
********************************************************* <
int32_t plat_is_smccc_feature_available(u_register_t fid) <
{ <
switch (fid) { <
case SMCCC_ARCH_SOC_ID: <
return SMC_ARCH_CALL_SUCCESS; <
default: <
return SMC_ARCH_CALL_NOT_SUPPORTED; <
} <
} <
<
/* Get SOC version */ /* Get SOC version */
int32_t plat_get_soc_version(void) int32_t plat_get_soc_version(void)
{ {
return (int32_t) return (int32_t)
(SOC_ID_SET_JEP_106(ARM_SOC_CONTINUATION_C | ((ARM_SOC_IDENTIFICATION_CODE << ARM_SOC_I
ARM_SOC_IDENTIFICATION | | (ARM_SOC_CONTINUATION_CODE << ARM_SOC_C
(FVP_SOC_ID & SOC_ID_IMPL_DEF_MASK)); | | FVP_R_SOC_ID);
} }
/* Get SOC revision */ /* Get SOC revision */
int32_t plat_get_soc_revision(void) int32_t plat_get_soc_revision(void)
{ {
unsigned int sys_id; unsigned int sys_id;
sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_I sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_I
return (int32_t)(((sys_id >> V2M_SYS_ID_REV_SHIFT) | return (int32_t)((sys_id >> V2M_SYS_ID_REV_SHIFT)
V2M_SYS_ID_REV_MASK) & SOC_ID_RE | V2M_SYS_ID_REV_MASK);
} }Tags
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Subscribers
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- Last Author
- garymorrison-arm
- Last Edited
- Jul 2 2021, 10:44 PM